Flash memory (as one of the nonvolatile memory devices) is getting general acceptance for use as a readily portable data storage device. The price per bit of flash memory is rapidly decreasing every year. The rate of price reduction is steeper than that anticipated from the design rule alone. This is due to improvements on the element structure and introduction of the idea of multiple-value storage. The conventional technology of large-capacity flash memory for file use is described in non-patent document Nos. 1 and 2. The former is concerned with a flash memory of NAND type with a small cell area. The latter is concerned with a flash memory of AND type suitable for multiple-value memory or multiple-bit memory which is achieved by controlling the number of electrons stored in the floating gate. Both types contribute to the reduction of cost per bit.
Another example of multiple-value memory is described in non-patent document 3. This document is concerned with an element in which the recording area is formed from SiN and hot electrons are used for charge injection. This device utilizes the phenomenon that hot electrons occur near the drain end and charge is captured by SiN traps (and hence charge accumulates near the injection point). It also utilizes both of the source end and the drain end as the charge storage regions by switching the voltage applied to the source and drain. Since writing in this manner requires a large current and the current supply from the power source is limited, it is not suitable for writing multiple bits at the same time in a file. Patent document 1 discloses writing by injection into the source side which is achieved by a lower drain current. This patent discloses a flash memory in which the inversion layer formed under the assist electrode is used as the wiring. This technology is designed to make the small cell area compatible with the assist electrode for injection at the source side.
[Patent Document 1]
JP-A No. 156275/2001
[Non-Patent Document 1]
“F. Arai et al., IEEE International Electron Devices Meeting” 2000, pp. 775–778
[Non-Patent Document 2]
“T. Kobayashi et al., IEEE International Electron Devices Meeting” 2001, pp. 29–32
[Non-Patent Document 3]
“B. Eitan et al., International Conference on Solid State Devices and Materials” 1999, p. 522–524